Electromigration is a known phenomenon resulting in the physical transport of atoms in a metal wire along the direction of electron flow. It is generally accepted that as electrons are conducted through the metal wire, they interact with imperfections in the molecular lattice of the metal and scatter. The scattering of the electrons causes thermal heating. Scattering and heating cause the atoms to vibrate. The vibration of the atoms creates additional electron scattering. The scattering results in momentum transfer from the electrons to the ions that make up the lattice of the metal wire material. The scattering and thermal heating increases with an increase in the current density passing through the metal wire. If the metal wire cannot properly dissipate the heat generated as a result of electron flow, the physical transport of atoms increases and the net motion of the atoms can cause failures in the metal wire through voiding or hillocking.
Voiding produces an open circuit in the metal wire. The electron density at the void increases because the electrons that comprise the current flow pass through a smaller cross section. The electron density increase further accelerates thermal heating and the voiding phenomenon until the metal wire can no longer conduct current. Hillocking is the opposite of voiding and refers to the phenomenon where excess metal is deposited in one area of the metal wire creating a spur. If the spur gets large, it can create a short circuit between the metal wire having the spur and its neighboring metal wire.
Due to continual miniaturization of VLSI circuits, the metal wires that are the electrical interconnects of an IC, are subject to increasingly higher current densities. These current densities approach and exceed the level that can cause electromigration. It is important, therefore, to design a circuit where all of the constituent metal interconnects carry a current density that is lower than the current density that causes electromigration.
Under the prior art, electromigration risk was managed by estimating direct current electromigration risk. Specifically, the maximum load capacitance per width of metal wire interconnect was used as the limit under which all metal wire interconnects in an IC were designed. The load capacitance for each metal wire interconnect in the IC design was estimated and kept under the calculated maximum. It is known that there are two types of electromigration phenomenon, direct current electromigration and alternating current electromigration. For formerly prevalent clock frequencies and wire widths, the direct current electromigration effects are a limiting factor and load capacitance is a reliable predictor of electromigration risk in an IC. As clock speeds increase and wire widths decrease, however, alternating current electromigration effects present a significant risk of electromigration. The alternating current electromigration risk cannot be reliably managed using the direct current electromigration risk estimates and approaches.
Accordingly, there is a need for a more accurate and reliable predictor of electromigration risk for high speed digital ICs when alternating current electromigration presents a higher risk to IC reliability.